SiFive, the start-up that raised $13.5 million for its open source silicon chip architecture RISC -V
【Summary】SiFive, the company creating a new open source model in the semiconductor business raises $13.5 million. The San Francisco-based company was founded in 2015, and its goal is to manufacture open source, custom designed silicon chips.
By Eric Walz
SiFive, the company creating a new open source model in the semiconductor business, has raised $8.5 million in a second round of funding, led by Spark Capital. Additionally, Osage University Partners and Sutter Hill Ventures helped to finance the new round. The new funding brings the total investment in SiFive to $13.5 million.
"At Spark Capital, we believe technology is the great equalizer," says Spark partner Todd Dagres, "SiFive's singular goal of putting custom chips into the hands of everyone from startups to exploratory design teams to inventors with a healthy crowdfunding campaign resonates with our core values."
The San Francisco-based company was founded in 2015, and its goal is to manufacture open source, custom designed silicon chips.
SiFive was founded by Krste Asanovic and Yunsup Lee. The two met when they were both EECS students at the University of California Berkeley. The founders, as well as others on their team, created RISC-V (pronounced "risk-five") as a new, open source instruction set architecture (ISA), also known as industry standard architecture.
Currently, tech giants such as microprocessor makers Intel and ARM, both have their own ISA's, which are closed source IP (intellectual property). For example, ARM's revenue comes entirely from IP licensing. The company relies upon ARM's licensees, partners, or customers to actually build and sell its chip.
SiFive takes a different approach, making their chip architecture open source and free with a simple BSD license. SiFive, as the inventor of RISC-V, intended to make RISC-V open and accessible to everyone.
RISC-V is set to be the standard open source architecture in all modern computing devices, from 32-bit embedded microcontrollers, to 64-bit application processors and datacenter accelerators and beyond, the company posted on its website.
Rather than having just one company own the ISA, SiFive's RISC-V is a free (reduced instruction set computing) platform. Instead of the income generated licensing their own ISA, the company's income will be through customization and support, similar to the way Linux companies do with their own unique versions of Linux, the most popular open source operating system.
So far, the RISC-V foundation has 60 supporting member companies, including Google, Microsoft, IBM, Qualcomm, NVIDIA, Samsung, Microsemi. SiFive has developed its Coreplex IP that other companies can license to design their own processors and computing systems based on RISC-V.
An introduction to the RISC-V computer architecture
RISC-V is a free and open instruction set architecture for modern microprocessors (chips). It consists of all of the software instructions needed to program a microprocessor based on the RISC-V architecture. SiFive is taking that architecture and making it custom designable for companies according to their needs.
SiFive has two Coreplex versions of its silicon microprocessors
E31 Coreplex - The most deployed RISC-V core in the world, the E31 Coreplex is designed for low power, high performance, 32-bit embedded applications such as Edge Computing, Smart IoT, or Wearables.
E51 Coreplex - A 64-bit embedded core, the E51 Coreplex is the ideal solution to act as a system or host control core inside larger 64-bit SoCs, as its small size and performance efficiency set it apart from the typical, bloated, and large 64-bit processors while still maintaining full software compatibility with mainstream software toolchains.
The SiFive Freedom Platform
All of SiFive's Freedom Un-leashed platforms are defined by a free and open platform specification, which promotes and encourages open-source software development. The verified base silicon platform allows SiFive to quickly and cost effectively customize and add features for individual customers, based on their needs. This provides companies with the power and flexibility of having custom silicon chips with access to the RISC-V software ecosystem.
The U500 platform is the first product of SiFive's Freedom family of customizable RISC-V SoCs (system on chip). Combining a configurable high-performance Unix-capable cache-coherent 64-bit multiprocessor with application-specific custom hardware, the Freedom Un-leashed line of silicon chips reduces non-recurring engineering costs (NRE), and time-to-market for customized SoCs in markets such as machine learning, storage and networking.
SiFive Freedom U500 Platform Technical Specifications
Each U500 SoC can include a SiFive U5 Coreplex with 1 to 8 64-bit, RISC-V cores with private control caches, a shared L2 cache, DDR3/DDR4 DRAM channels, DualMode PCIe Gen 3.0, 1Gb Ethernet, USB 3.0, platform-level interrupt controller, an on-chip debug unit, as well as an extensive selection of other peripheral devices.
Additionally, the U5 RISC-V Coreplex can be configured with up to eight, 64-bit cache-coherent U5 application cores. Each U5 core has a high-performance single-issue in-order 64-bit execution pipeline, with a peak sustained execution rate of one instruction per clock cycle.
U500 cores include a comprehensive dynamic branch prediction scheme, including branch target buffers (BTB), and branch history tables (BHT), and return-address stacks to improve system overall performance.
The SiFive U500 System on Chip (SoC)
The cores support the standard RV64IMAFD ISA, including full hardware support for single and double-precision IEEE 754-2008 floating-point with fully pipelined fused multiply-adders, a hardware divide and square-root unit, and full hardware support for subnormal numbers. A hardware integer multiplier and divider is also provided.
SiFive provides a full open-source RISC-V software development for the U500 SoCs including a full Linux port with device drivers for the supported devices ,modern C and C++ compilers, standard libraries, assemblers, linkers, together and debug tools.
The 2017 Shanghai RISC-V Workshop
The 6th RISC-V Workshop, which is co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai, China takes place on May 8-11, 2017, has attracted much interest and the event is sold out.
The goal of the workshop is to bring the global RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of SiFive's reduced instruction set computing platform.
Over the past year the SiFive's RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world applications. In the near future, many companies might introduce commercial products that implement SiFive's RISC-V architecture.
Originally from New Jersey, Eric is a automotive & technology reporter covering the high-tech industry in Silicon Valley. Eric has over 15 years of automotive experience and a bachelors degree in computer science. These skills, combined with technical writing and news reporting, allows him to fully understand and identify new and innovative technologies in the auto industry and beyond. He has worked at Uber on self-driving cars and as a technical writer, helping people to understand and work with technology. Outside of work, Eric likes to travel to new places, play guitar, and explore the outdoors.
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